AMD Horus

to get instant updates about 'AMD Horus' on your MyPage. Meet other similar minded people. Its Free!


All Updates

The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way (CPU sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.

The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based around the InfiniBand standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By putting the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding), this system has an effective internal speed of 30 Gbit/s.

With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a...
Read More

No feeds found

Posting your question. Please wait!...

No updates available.
No messages found
Suggested Pages
Tell your friends >
about this page
 Create a new Page
for companies, colleges, celebrities or anything you like.Get updates on MyPage.
Create a new Page
 Find your friends
  Find friends on MyPage from