Column Address Strobe (CAS) latency
, or CL
, is the delay time between the moment a memory controller
tells the memory module to access a particular memory column
on a RAM
memory module, and the moment the data from given array location is available on the module's output pins. In general, the lower the CAS latency, the better.
In asynchronous DRAM
, the interval is specified in nanoseconds. In synchronous DRAM
, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of an arbitrary time, the actual time for an SDRAM
module to respond to a CAS event might vary between uses of the same module if the clock rate differs.
RAM operation background
Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line
. Sending a logical high signal along a given row enables the MOSFETs
present in that row, connecting each storage capacitor to its corresponding vertical bit line
. Each bit line is connected to a sense amplifier
which amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh
When no word line is active, the array is idle and the bit lines are held in a precharged
state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.
To access memory, a row must first be... Read More