Jazz DSP

<!-- Deleted image removed: -->The Jazz DSP, by , is a VLIW embedded digital siginal processor architecture with a 2-stage instruction pipeline, and single-cycle execution units. The baseline DSP includes one arithmetic logic unit (ALU), dual memory interfaces, and the control unit (instruction decoder, branch control, task control). Most aspects of the architecture, such as the number and sizes of Memory Interface Units (MIU) or the types and number of Computation Units (CU), datapath width (16 or 32-bit), the number of interrupts and priority levels, and debugging support may be independently configured using a proprietary graphical user interface (GUI) tool. A key feature of the architecture allows the user to add custom instructions and/or custom execution units to enhance the performance of their application.

Typical Jazz DSP performance can exceed 1000 million operations per second (MOPS) at a modest 100 MHz clock frequency. Please refer to the site for more details on Jazz DSP performance as compared to other benchmarked processors.


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